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ST92F120JR9T データシート(PDF) 314 Page - STMicroelectronics

部品番号 ST92F120JR9T
部品情報  8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD
PDF  320 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST92F120JR9T データシート(HTML) 314 Page - STMicroelectronics

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ST92F120 - ELECTRICAL CHARACTERISTICS
J1850 BYTE LEVEL PROTOCOL DECODER TIMING TABLE
(VDD =5V ± 10%, TA = –40°C to +105°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified)
Note:
(1) Values obtained with internal frequency at 24 MHz (INTC LK), with CLKSEL Register set to 23.
(2) In Transmission Mode, symbol durations are compliant to nominal values defined by the J1850 Protocol Specifications.
(3) All values are reported with a precision of
±1 µs.
J1850 PROTOCOL TIMING
Symbol
Parameter
Value
Unit
Note
Receive Mode
Transmission Mode
Min
Max
Nominal
TF
Symbols Filtered
0
≤ 7-
µs
(1)(2)
TIB
Invalid Bit Detected
> 7
≤ 34
-
µs
(1)(2)
TP0
Passive Data Bit “0”
> 34
≤ 96
64
µs
(1)(2)(3)
TA0
Active Data Bit “0”
> 96
≤ 163
128
µs
(1)(2)(3)
TP1
Passive Data Bit “1”
> 96
≤ 163
128
µs
(1)(2)(3)
TA1
Active Data Bit “1”
> 34
≤ 96
64
µs
(1)(2)(3)
TNBS
Short Normalization Bit
> 34
≤ 96
64
µs
(1)(2)(3)
TNBL
Long Normalization Bit
> 96
≤ 163
128
µs
(1)(2)(3)
TSOF
Start Of Frame Symbol
> 163
≤ 239
200
µs
(1)(2)(3)
TEOD
End Of Data Symbol
> 163
≤ 239
200
µs
(1)(2)(3)
TEOF
End Of Frame Symbol
> 239
-
280
µs
(1)(2)(3)
TBRK
Break Symbol
> 239
-
300
µs
(1)(2)(3)
TIDLE
Idle Symbol
> 280
-
300
µs
(1)(2)(3)
T NBS
T A1
T P0
T EOD
T SOF
VPWO
T IDLE
T EOF
T EOD
VPWO
T IDLE
T EOF
T A0
T P1
T A1
T P0
T SOF
T A0
T P1
T NBL
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