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ST92F120JR9T データシート(PDF) 316 Page - STMicroelectronics |
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ST92F120JR9T データシート(HTML) 316 Page - STMicroelectronics |
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316 / 320 page  316/320 ST92F120 - ELECTRICAL CHARACTERISTICS A/D CHANNEL ENABLE TIMING TABLE (VDD =5V ± 10%, TA = –40°C to +105°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, standard timer prescaler and counter programmed values. The value in the right hand two columns show the timing minimum and maximum for an internal clock (INTCLK) at 24MHz. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2*OSCIN period when OSCIN is divided by 2; OSCIN period / PLL factor when the PLL is enabled. n = number of autoscanned channels (1 ≤ n ≤ 8) A/D CHANNEL ENABLE TIMING N ° Symbol Parameter Value (Note) Unit Formula Min. Max. 1TwEXT CEn Pulse width 138 x n x Tck n x 5.75 - µs 1 |
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