Operating modes

M41ST84W

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2.2

READ mode

In this mode the master reads the M41ST84W slave after setting the slave address (see

Figure 8). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word

address ‘An’ is written to the on-chip address pointer. Next the START condition and slave

address are repeated followed by the READ mode control bit (R/W=1). At this point the

master transmitter becomes the master receiver. The data byte which was addressed will be

transmitted and the master receiver will send an acknowledge bit to the slave transmitter.

The address pointer is only incremented on reception of an acknowledge clock. The

M41ST84W slave transmitter will now place the data byte at address An+1 on the bus, the

master receiver reads and acknowledges the new byte and the address pointer is

incremented to “An+2.”

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter (see Figure 9 on page 15).

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume either due to a stop condition or when

the pointer increments to a non-clock or RAM address.

Note:

This is true both in READ mode and WRITE mode.

An alternate READ mode may also be implemented whereby the master reads the

M41ST84W slave without first writing to the (volatile) address pointer. The first address that

is read is the last one stored in the pointer (see Figure 10 on page 15).

Figure 8.

Slave address location

AI00602

R/W

SLAVE ADDRESS

START

A

0

100

0

11