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74VHC238TTR データシート(PDF) 1 Page - STMicroelectronics

部品番号 74VHC238TTR
部品情報  3 TO 8 LINE DECODER
PDF  12 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

74VHC238TTR データシート(HTML) 1 Page - STMicroelectronics

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November 2004
s
HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 5V
s
LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s
POWER DOWN PROTECTION ON INPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 238
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHC238 is an advanced high-speed
CMOS 3 TO 8 LINE DECODER fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go high. If enable input G1 is held low or either
G2A or G2B is held high, decoding function is
inhibited and all the 8 outputs go to low.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All
inputs
and
outputs
are
equipped
with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC238
3 TO 8 LINE DECODER
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE
T & R
SOP
74VHC238MTR
TSSOP
74VHC238TTR
TSSOP
SOP
Rev. 4


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