TDA7580_07 datasheet(13/39 Pages) STMICROELECTRONICS

13 / 39 page

TDA7580

Block diagram and electrical specifications

13/39

GNDH

3.3V IO ring power ground (debug

interface, GPIO)

VDDH

3.3V IO ring power supply (Debug

interface, GPIO)

DBCK1

DSP1 debug port clock (DBCK1) if HS3I

master mode, else high speed

synchronous serial interface (HS3I)

channel3 data

DSP1 GPIO9. 5V

tolerant. With internal

pull down, on at reset

[PP]

Input

DBIN1

DSP1 GPIO or DSP1 debug port data in

(DBIN1) if HS3I master mode, else high

speed synchronous serial interface (HS3I)

channel2 data i

DSP1 GPIO11

5V tolerant

With internal pull down,

on at reset [PP]

Input

DBRQ1

DSP1 GPIO or DSP1 debug port request

(DBRQ1) if HS3I master mode, else high

speed synchronous serial interface (HS3I)

channel1 data

5V tolerant. With

internal pull up, on at

reset [PP]

Input

DBOUT1

DSP1 GPIO or DSP1 debug port data out

(DBOUT1) if HS3I master mode, else high

speed synchronous serial interface (HS3I)

clock

DSP1 GPIO10

5V tolerant

With internal pull up, on

at reset [PP]

Input

VDD

Digital core power supply

1.8V

GND

Digital core power ground

VDDISO

3.3V N-isolation biasing supply

Clean 3.3V supply to be

star connected to

voltage regulator

GNDH

3.3V IO ring power ground

(modulator digital section)

VDDH

3.3V IO ring power supply

(modulator digital section)

VDDSD

3.3V IFADC modulator analogue power

supply

Clean power supply, to

be star connected to

3.3V voltage regulator

Table 5.

Pin description (continued)

N°

Name

Type

Description

Notes

After

Reset

I/O Type

I/O Definition and status

P: Power supply from voltage regulator

G: Power ground from voltage regulator

A: Analogue I/O

I: Digital input

O: Digital output

B: Bidirectional I/O

Z: high impedance (input)

O: logic low output

X: undefined output

1: logic high output

Output PP: Push pull / OD: Open drain

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