1/13

July 2001

s

HIGH SPEED :

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

WIDE OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 259

DESCRIPTION

The M74HC259 is an high speed CMOS 8 BIT

ADDRESSABLE LATCH fabricated with silicon

The M74HC259 has single data input (D) 8 latch

outputs (Q0-Q7), 3 address inputs (A, B, and C),

common enable input (E), and a common CLEAR

input. To operate this device as an addressable

latch, data is held on the D input, and the address

of the latch into which the data is to be entered is

held on the A, B, and C inputs. When ENABLE is

taken low the data flows through to the addresses

output. The data is stored on the positive-going

edge of the ENABLE pulse. All unaddressed

latches will remain unaffected. With ENABLE in

the high state the device is deselected and all

latches remain in their previous state, unaffected

by changes on the data or address inputs. To

eliminate the possibility of entering erroneous data

into the latches, the ENABLE should be held high

(inactive) while the address lines are changing. If

ENABLE is held high and CLEAR is taken low all

eight latches are cleared to the low state. If

ENABLE is low all latches except the addressed

latch will be cleared. The addressed latch will

instead

follow

the

D

input,

effectively

implementing a 3-to-8 line decoder.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M74HC259

8 BIT ADDRESSABLE LATCH

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

TUBE

T & R

DIP

M74HC259B1R

SOP

M74HC259M1R

M74HC259RM13TR

TSSOP

M74HC259TTR

TSSOP

DIP

SOP