STE2007_06 datasheet(13/62 Pages) STMICROELECTRONICS

13 / 62 page

STE2007

Electrical characteristics

13/62

3.5

Driver TxData mode

Note:

Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is always 3-8ns

before SCLK pulse falling edge

The input signal rise and fall times must be within 10ns.

Every timing is specified on the basis of 30% and 70% of VDDI.

Note:

The input signal rise and fall times must be within 10ns.

Every timing is specified on the basis of 30% and 70% of VDDI.

Table 11.

Input signals change time

Signal

Symbol

Parameter

Min.

Typ.

Max.

Unit

Inputs

tr,tf

(1)

To 30% & 70% levels

Table 12.

Timings based on 4 MHz SCLK speed

Symbol

Item

Condition

Min.

Typ.

Max.

Units

Data hold time

Note 1

100

125

Access time

–

100

Output disable time

–

100

Data setup time

–

100

–

!CS pulse width high

–

250

Table 13.

Timings based on 1 MHz SCLK speed

Symbol

Item

Condition

Min.

Typ.

Max.

Units

Data hold time

–

100

125

Access time

–

450

Output disable time

–

450

Data setup time

–

100

–

1CS pulse width high

–

250

STE2007 データシート(PDF) 13 Page - STMicroelectronics

STE2007 データシート(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

データシートダウンロード

リンク URL

STE2007 データシート(PDF) 13 Page - STMicroelectronics

STE2007 データシート(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

データシート ダウンロード

リンク URL

データシートダウンロード