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STPC4EDBC データシート(PDF) 39 Page - STMicroelectronics

部品番号 STPC4EDBC
部品情報  X86 Core PC Compatible Information Appliance System-on-Chip
PDF  93 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPC4EDBC データシート(HTML) 39 Page - STMicroelectronics

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ELECTRICAL SPECIFICATIONS
Release 1.5 - January 29, 2002
39/93
4.5.2 RESET SEQUENCE
Figure 4-4 describes the reset sequence of the
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
Figure 4-4. Reset timing diagram
S trap O ptions
SYSRSTI#
SYSRSTO #
14 M Hz
VA LID CONFIG URATIO N
HCLK
PCI_CLK
2.3 m s
IS AC LK
1.6 V
MD[63:0]



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