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STSR3 データシート(PDF) 5 Page - STMicroelectronics |
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STSR3 データシート(HTML) 5 Page - STMicroelectronics |
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5 / 12 page ![]() STSR3 5/12 TIMING DIAGRAM APPLICATION INFORMATION: STSR3 IN FLYBACK CONVERTER SECONDARY SIDE NOTES 1) Ceramic Capacitors C1 and C2 must be placed very close to the IC; 2) R1 andR2set theanticipationtimeby partitioning theVCC voltage; 3) R3 and R4 is a resistor divider meant to provide the correct CK voltage range; 4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high; 5) D1 could be necessary to protect INHIBIT pin from negative voltages. 6) D2 could be necessary to protect INHIBIT pin from voltages higher than VCC 7) D3 could be necessary to protect CK pin from voltages higher than VCC. 8) SGLGND layout trace must not include OUTGATE current paths. 9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike. +5V +5V Vout Vin +5V Cout C2 100nF R1 R2 R3 R4 D1 D2 C1 100nF R5 STSR3 4 6 3 Ck SGLGND SETANT TRANSFORMER MosfetN D3 PWM Feedback Loop option |
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