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STV0196B データシート(PDF) 14 Page - STMicroelectronics |
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STV0196B データシート(HTML) 14 Page - STMicroelectronics |
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14 / 23 page ![]() ABSOLUTE MAXIMUM RATINGS Maximum limits indicate where permanent device damages occur, continuous operation at these limits is not intended and should be limited to those conditions specified in section ”DC Electrical Specifications”. Symbol Parameter Value Unit VDD Power Supply (1) -0.3 to 4 V VI Voltage on Input pins (2) -0.3 to VDD + 0.3 V Vo Voltage on Output pins -0.3 to VDD +0.3 V Tstg Storage Temperature -40 to +150 oC Toper Operating Ambient Temperature -10 to +85 oC PD Power Dissipation 1.5 W Notes : 1. All VDD to be tied together 2. SCL, SDA, NRES Pins can be tied to 5V ± 10% with an impedance ≥ 2kΩ (remark in these conditions the input leakage current becomes higher than 10 µA). DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V, Tamb =25 oC unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VDD Operating Voltage 0 oC ≤ Toper ≤ 70oC 0 oC< Toper <85oC, M_CLK ≤ 55MHz 3.0 3.15 3.3 3.3 3.6 3.45 V V IDD Average Power Supply Current CLOAD = 20pF on all outputs, M_CLK = 60MHz 300 480 mA VIL VIH Input Logic Low Voltage except M_CLK Input Logic High Voltage except M_CLK M_CLK = 60MHz -0.3 2.0 0.8 3.6 V V VIL VIH Input Logic Low Voltage for M_CLK Input Logic High Voltage for M_CLK M_CLK = 60MHz -0.3 2.2 0.8 3.6 V V ILK Input Leakage Current VIN = 0V and VDD 10 µA CIN Input Capacitance 3.5 pF VOL VOH Output Logic Low Voltage Output Logic High Voltage CLOAD = 20pF, ILOAD = 2mA, M_CLK = 60MHz 2.4 0.5 V V Note :This product doesn’t withstand the MIL 883C Norm at 2kV, but only at 1.5kV (all VDD tied together). TIMING CHARACTERISTICS Symbol Parameter Min. Typ. Max. Unit PRIMARY CLOCK (see Figure 4) tM_CLK Master Clock Period 0 oC ≤ Toper ≤ 70oC 0 oC< Toper <85oC 16.6 18.2 ns ns tHIGH Clock High Time 6 ns tLOW Clock Low Time 6 ns tR Clock Rising Edge 4ns tF Clock Falling Edge 4ns I[5:0],Q[5:0] INPUT SPECIFICATION S (see Figure 5) tSU I,Q stable before M_CLK 4 ns tH I,Q stable after M_CLK 4 ns D60 OUTPUT CHARACTERISTICS (see Figure 6) t60 D60 period (Tm_clk * 60) -10 (Tm_clk*60) +10 ns D[7:0],D/P,CK_OUT ,STR_OUT,ERROR OUTPUT CHARACTERISTICS Bit RS1 = 1 in register RS ( adr = 0x0A) (see Figure 7) tCKSU D[7:0],D/P,STR_OUT,ERROR stable before CK_OUT Falling Edge 32 ns tCKH D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Falling Edge 32 ns Bit RS1 = 0 in register RS ( adr = 0x0A) (see Figure 8) tCKSU D[7:0],D/P,STR_OUT,ERROR stable before CK_OUT Rising Edge 32 ns tCKH D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Rising Edge 32 ns STV0196B 14/23 |
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