STV9410 datasheet(16/25 Pages) STMICROELECTRONICS

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Active Area

Margin

H Pulse

Margin

H Pulse

DESIGNATION

PIXEL CLOCK

Y OUTPUT

SYNC IN

VERTICAL

PULSE

F(8 : 0)

COMMENTS

Sampling

Clock

S = 0 clear

F (8 : 0) only

Sampling on

first pixel of

active area

TIMING DIAGRAM

VERTICAL SYNCHRONIZATION

DESIGNATION

PIXEL CLOCK

COMMENTS

Sampling

Clock

TIMING DIAGRAM

HORIZONTAL SYNCHRONIZATION

L= L + 1

L= L

INTERNAL H SYNC

DURATION = L (5 : 0)

EXTERNAL H SYNC

UNLOCKED

EXTERNAL H SYNC

LOCKED

Sampling window

for H Synchro

Line Duration

Increase + 1

Good

Line Duration

Figure 11 : Synchronization on SYNC IN External Signal

3. INTERNAL REGISTER DESCRIPTION

STV9410 is programmable with 7 registers of 16

bit each. These registers can also be programmed

in byte mode. Not significant bit must be cleared in

order to be compatible with next generation prod-

ucts.

3.1 TIME BASE REGISTERS

Registers VERT, HORI, HSYN and PORT are de-

scribed in chapter 2.3

3.2 ADDRESS REGISTER (ADDR )

Internal address : 2FF9-2FF8 h

RESET value :00-00 h

(@ = RESET default configuration)

2FF9 h

P12 P11 P10

0000

2FF8 h

G12 G11 G10

A12 A11 A10

0000

P(12:6) : Page first descriptor address, P(5:0)=0 @

G(12:10) : Graphic character set MSB address,

G(9:0)=0 @

A(12:10) : Alphanumeric character set MSB address,

A(9:0)=0 @

NB : as addresses are in RAM area, address bit 13

is reset to ”0”

STV9410

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