TIMINGS

Symbol

Parameter

Min.

Typ.

Max.

Unit

OSCILATOR INPUT : XTI (see Figure 2)

Clock High Level

20

ns

Clock Low Level

20

ns

Clock Frequency

TBD

15

MHz

Pixel Frequency

50

MHz

RESET

Reset Low Level Pulse

4

µs

Rise Time (Note 1)

5

ns

Fall Time (Note 1)

5

ns

Skew between R, G, B, FBLK (Note 1)

5

ns

I

SCL Clock Frequency

0

1

MHz

Time the bus must be free between 2 access

500

ns

Hold Time for Start Condition

500

ns

Set up Time for Stop Condition

500

ns

The Low Period of Clock

400

ns

The High Period of Clock

400

ns

Hold Time Data

0

ns

Set up Time Data

375

ns

Fall Time of SDA

20

ns

Rise Time of Both SCL and SDA

Depend on the pull-up resistor

and the load capacitance

Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes

characterization on batches comming from corners of our processes and also temperature characterizat ion.

XTI

TWH

TWL

Figure 2

SDA

SCL

T

HDAT

STOP

START

DATA

STOP

Figure 3

STV9425 - STV9425B - STV9426

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