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H8SX1663 データシート(PDF) 357 Page - Renesas Technology Corp |
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H8SX1663 データシート(HTML) 357 Page - Renesas Technology Corp |
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357 / 1158 page ![]() Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 305 of 1102 REJ09B0294-0100 If an external bus release request, external access, and a refresh request occur simultaneously, the order of priority is as follows: Refresh > External bus release > External access by CPU, DTC, and DMAC 6.13.2 Pin States in External Bus Released State Table 6.32 shows pin states in the external bus released state. Table 6.32 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance BS High impedance CSn (n = 7 to 0) High impedance AS High impedance AH High impedance RD/ WR High impedance LUCAS, LLCAS High impedance RD High impedance RAS High impedance CAS High impedance WE High impedance DQMLU, DQMLL High impedance CKE High impedance OE High impedance LUB, LLB High impedance LHWR, LLWR High impedance DACKn (n = 3 to 0) High |
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