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H8SX1663 データシート(PDF) 392 Page - Renesas Technology Corp |
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H8SX1663 データシート(HTML) 392 Page - Renesas Technology Corp |
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392 / 1158 page ![]() Section 7 DMA Controller (DMAC) Rev.1.00 Jun. 07, 2006 Page 340 of 1102 REJ09B0294-0100 Bit Bit Name Initial Value R/W Description 4 3 2 1 0 DARA4 DARA3 DARA2 DARA1 DARA0 0 0 0 0 0 R/W R/W R/W R/W R/W Destination Address Extended Repeat Area Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 7.3 shows the settings and areas of the extended repeat area. |
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