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H8SX1663 データシート(PDF) 815 Page - Renesas Technology Corp

部品番号 H8SX1663
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX1663 データシート(HTML) 815 Page - Renesas Technology Corp

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Section 16 USB Function Module (USB)
Rev.1.00 Jun. 07, 2006 Page 763 of 1102
REJ09B0294-0100
16.3.8
Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 1
(ISR1).
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
EP3 TR
0
R/W
1
EP3 TS
0
R/W
0
VBUSF
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
6
5
4
3
0
0
0
0
0
R
R
R
R
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
EP3 TR
0
R/W
EP3 Transfer Request
1
EP3 TS
0
R/W
EP3 Transmission Complete
0
VBUSF
0
R/W
USB Bus Connect
16.3.9
Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 2
(ISR2).
Bit
Bit Name
Initial Value
R/W
7
SSRSME
0
R/W
6
0
R
5
0
R
4
SURSE
0
R/W
3
CFDN
0
R/W
2
0
R
1
SETCE
0
R/W
0
SETIE
0
R/W



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