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M16C/26 データシート(PDF) 50 Page - Renesas Technology Corp |
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M16C/26 データシート(HTML) 50 Page - Renesas Technology Corp |
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50 / 239 page ![]() Renesas Technology Corp. Interrupts 44 M16C/26 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Under development Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. • Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. • Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Figure 1.9.1. Classification of interrupts Interrupt Software Hardware Special Peripheral I/O (Note) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI DBC Watchdog timer Single step Address matched Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Interrupts Type of Interrupts Figure 1.9.1 lists the types of interrupts. |
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