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TDA7512

1.7

PLL and IF Counter Section

1.7.1

PLL Frequency Synthesizer Block

This part contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is required

to build a complete PLL system for FM world tuning and AM upconversion. For auto search stop operation an

IF counter system is available.

The counter works in a two stages configuration. The first stage is a swallow counter with a two modulus (32/33)

precounter. The second stage is an 11-bit programmable counter.

The circuit receives the scaling factors for the programmable counters and the values of the reference frequen-

followed by the reference divider. The main reference and step-frequencies are free selectable (RC, PC).

Output signals of the phase detector are switching the programmable current sources. The loop filter integrates

their currents to a DC voltage.

To minimize the noise induced by the digital part of the system, a special guard configuration is implemented.

The loop gain can be set for different conditions by setting the current values of the chargepump generator.

1.7.2

Frequency Generation for Phase Comparison

The RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5-bit A-divider. The

5-bit register (PC0 to PC4) controls this divider. In parallel the output of the prescaler connects to an 11-bit B-

divider. The 11-bit PC register (PC5 to PC15) controls this divider

Dividing range:

Important: For correct operation: A

1.7.3

Three State Phase Comparator

This phase error signal drives the charge pump current generator.

1.7.4

Charge Pump Current Generator

This system generators signed pulses of current. The phase error signal decides the duration and polarity of

those pulses. The current absolute values are programmable by A register for high current and B register for

low current.

1.7.5

Inlock Detector

Switching the chargepump in low current mode can be done either via software or automatically by the inlock

detector, by setting bit LDENA to "1".

After reaching a phase difference about lower than 40nsec the chargepump is forced in low current mode. A

1.7.6

Low Noise CMOS Op-amp

An internal voltage divider at pin VREF2 connects the positive input of the low noise op-amp. The charge pump

output connects the negative input. This internal amplifier in cooperation with external components can provide

an active filter. The negative input is switchable to three input pins, to increase the flexibility in application. This

feature allows two separate active filters for different applications.

While the high current mode is activated LPHC output is switched on.

1.7.7

IF Counter Block

The aim of IF counter is to measure the intermediate frequency of the tuner for AM and FM mode. The input

signal for FM and AM upconversion is the same 10.7MHz IF level after limiter. AM 450KHz signal is coming from