TS68230 datasheet(18/61 Pages) STMICROELECTRONICS

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PORT MODES

This section contains information that distinguishes

the various port modes and submodes. General

characteristics common to all modes are defined in

Section 2 Port General Information and Conven-

tions. A description of the port A control register

(PACR) and port B control register (PBCR) is given

before each mode description. After each submode

description, the programmable options are listed for

that submode.

3.1. PORT A CONTROL REGISTER (PACR)

The port A control register, in conjunction with the

programmed mode and the port B submode,

controls the operation of port A and the handshake

pins H1 and H2. The port A control register contains

five fields : bits 7 and 6 specify the port A submode ;

bits 5, 4, and 3 control the operation of the H2 hand-

shake pin and the H2S status bit ; bit 2 determines

whether an interrupt will be generated when the H2S

status bit goes to one ; and bit 1 determines whether

a service request (interrupt request or DMA request)

will occur ; bit 0 controls the operation of the H1S sta-

tus bit. The PACR is always readable and writable.

All bits are cleared to zero when the RESET pin is

asserted. When the port A submode field is relevant

in a mode/submode definition, it must not be altered

unless the H12 enable bit in the port general control

this document). Altering these bits will give unpre-

dictable results.

3.2. PORT B CONTROL REGISTER (PBCR)

The port B control register specifies the operation of

port B and the handshake pins H3 and H4. The port

B control register contains five fields : bits 7 and 6

specify the port B submode ; bits 5, 4, and 3 control

the operation of the H4 handshake pin and H4S sta-

tus bit ; bit 2 determines whether an interrupt will be

generated when the H4S status bit goes to a one ;

bit 1 determines whether a service request (interrupt

request or DMA request) will occur ; and bit 0

controls the operation of the H3S status bit. The

PBCR is always readable and writable. There is ne-

ver a consequence to reading the register.

All bits are cleared to zero when the RESET pin is

asserted. When the port B submode field is relevant

in a mode/submode definition, it must not be altered

unless the H34 enable bit in the port general control

this document).

3.3. MODE 0 - UNIDIRECTIONAL 8-BIT MODE

In mode 0, ports A and B operate independently.

Each may be configured in any of its three possible

submodes :

Submode 00 - Pin-Definable Double-Buffered In-

put or Single-Buffered Output

Submode 01 - Pin-Definable Double-Buffered

Output or Non-Latched Input

Submode 1X - Bit I/O (Pin-Definable Single-Buf-

fered Output or Non-Latched Input)

Handshake pins H1 and H2 are associated with port

A and configured by programming the port A control

control register enables port A transfers). Hand-

shake pins H3 and H4 are associated with port B

and configured by programming the port B control

control register enables port B transfers). The port

A and B data direction registers operate in all three

submodes. Along with the submode, they affect the

data read and write at the associated data register

according to table 3.1. They also enable the output

buffer associated with each port pin. The DMAREQ

pin may be associated with either (not both) port A

or port B, but does not function if the bit I/O submode

(submode 1X) is programmed for the chosen port.

6543

Port A

Submode

H2 Control

Interrupt

Enable

SVCRQ

Enable

Status

Control

6543

Port B

Submode

H4 Control

Interrupt

Enable

SVCRQ

Enable

Status

Control

SECTION 3

TS68230

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