SSL1750_1

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 01 — 15 September 2008

11 of 29

NXP Semiconductors

SSL1750

SMPS control IC for LED drivers

7.2.6 Burst mode control

When the output power of the flyback converter (see Section 7.3) is low, the flyback

converter switches over to frequency reduction mode. When frequency reduction mode is

entered by the flyback controller, the power factor correction circuit switches to burst mode

control.

In burst mode control, switching of the power factor correction circuit is inhibited until the

to avoid audible noise (see Section 7.2.5). As soon as the voltage on pin VOSENSE

soft-stop time the output voltage of the power factor correction circuit overshoots,

not reach the normal operation output voltage of the power factor correction circuit in a

typical application due to this overshoot.

The burst mode repetition rate is defined by the output power and the value of the bus

During burst mode operation pin PFCCOMP is clamped between a voltage of 2.7 V (typ)

and 3.9 V (typ). The lower clamp voltage limits the maximum power that is delivered

during burst mode operation and yields a more sinusoidal input current during the burst

pulse. The upper clamp voltage ensures that the PFC can return to its normal regulation

point in a limited amount of time when returning from burst mode.

As soon as the flyback converter leaves frequency reduction mode, the power factor

correction circuit restores normal operation. To prevent continuous on and off switching of

the PFC circuit, a small hysteresis has been built in (50 mV (typ) on pin FBCTRL).

Fig 6.

Soft start-up and soft-stop of PFC

SOFT START

SOFT STOP

CONTROL

OCP

+

11

PFCSENSE

0.5 V

Istart(soft)PFC

≤ 60 µA

S1

RSS1

CSS1

RSENSE1

014aaa018