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CS8422-DNZ データシート(PDF) 69 Page - Cirrus Logic |
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CS8422-DNZ データシート(HTML) 69 Page - Cirrus Logic |
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69 / 82 page  DS692PP1 69 CS8422 12.6 Jitter Tolerance Figure 36 shows the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specifi- cation. CS8422 devices have been tested to pass this template. 12.7 Group Delay The group delay introduced by the CS8422 depends on the type of interface selected, and input and output sample rates of the sample rate converter. The expression for the group delay through the CS8422 with the use of the sam- ple rate converter is shown below, where the interface delay is 3 OLRCK periods in all modes except AES3 direct mode, in which it is 2 OLRCK periods. If the sample rate converter is not being used, then the approximate group delay will be equal to the interface delay. Figure 36. Jitter Tolerance Template TotalGroupDelay 8.7 Fsi -------- 5 Fso --------- InterfaceDelay ++ ⎝⎠ ⎛⎞ = |
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