© 2003 by Eureka Technology Inc.

4962 El Camino Real,

Los Altos, CA 94022, USA

Tel: 1 650 960 3800

Fax: 1 650 960 3805

http://www.eurekatech.com

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Eureka Technology

• Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740,

750 and 8260.

• Automatic bus arbitration for address bus and data bus based on internal bus

request.

• Separate address bus and data bus tenure with individual grant signals.

• Supports address bus retry and data transfer error.

• Qualified address bus grant and data bus grant through the use of bus busy sig-

nals.

• User specified burst data transfer and single beat data transfer.

• Supports two back-end user request ports with built-in arbitration.

• Efficient back-end bus for internal data transfer.

• Supports bus parking.

• Designed for ASIC or programmable logic device implementations in various

system environments.

• Fully static design with edge triggered flip-flops.

• Optimized for Actel SX-A, RTSX-S, AX, and APA product families.

EP201 PowerPC Bus Master

FEATURES

Address

retry restart

Product Summary

PowerPC Host Bus

Data

tenure

Address

tenure

Arbitration logic

for user bus

Dual User Interface