APA600-FGGES datasheet(52/174 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

1- 46

v5.7

Input Buffer Delays

Figure 1-28 • Input Buffer Delays

Table 1-33 • Worst-Case Commercial Conditions

VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C

Macro Type

Description

Max. tINYH

Max. tINYL

Units

Std.

–F

Std.

–F

IB33

3.3 V, CMOS Input Levels3, No Pull-up Resistor

0.4

0.5

0.6

0.7

IB33S

3.3 V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger

0.6

0.7

0.8

0.9

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP=2.3 V for delays.

5. All –F parts are only available as commercial.

Table 1-34 • Worst-Case Commercial Conditions

VDDP = 2.3 V, VDD = 2.3 V, TJ = 70°C

Macro Type

Description

Max. tINYH

Max. tINYL

Units

Std.

–F

Std.

–F

IB25LP

2.5 V, CMOS Input Levels3, Low Power

0.9

1.1

0.6

0.8

IB25LPS

2.5 V, CMOS Input Levels3, Low Power, Schmitt Trigger

0.7

0.9

1.1

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP=2.3 V for delays.

5. All –F parts are only available as commercial.

PAD

DDP

0 V

50%

GND

50%

INYH

50%

IN YL

IBx

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