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LTC2928IG データシート(PDF) 21 Page - Linear Technology |
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LTC2928IG データシート(HTML) 21 Page - Linear Technology |
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21 / 32 page ![]() LTC2928 21 2928f Forcing Supplies Off or Disabling Unused Channels The most convenient way to mask an unused channel is to tie its respective RT input to ground. After sequenc- ing begins, any enable output (EN) may be pulled low permanently by driving the respective RT input to ground (asynchronous OFF command). An asynchronously OFF channel cannot be re-enabled until a new sequence-up procedure is started. Any channel that is asynchronously OFF is removed from participation in the sequencing and supply monitoring processes, allowing the LTC2928 to operate normally on the remaining operating channels. When experiencing a fault in the “No Shutdown Debug Mode”, the asynchronous OFF feature may be used to conveniently pull down the enable outputs. Alternatively, VCC may be turned off and on again. Clearing a fault con- dition requires the ON input to be low while the supplies are below their sequence-down thresholds. Forcing Supplies On Prior to Sequencing Prior to sequencing, any or all enable pins may be forced high by pulling the respective RT pin to VCC. In this man- ner, supplies may be tested individually or together in any combination.WithanyRTpinatVCC,therespectivevoltage monitorinputsandcomparatoroutputsbecomeactivewith thresholds parked at the configured sequence-up thresh- old. Outside of sequencing, RST (with 100% thresholds selected) and OV are always functional, regardless of RT pin state. If all four RT pins are at VCC, the LTC2928 can be used as a stand-alone quad voltage monitor with under- and overvoltage indication as shown in Figure 11 (100% thresholds). With ON low in the RT forcing mode, sequence,commandandresetfaultsdonotoccur.External faultshowever,maybedetected(overvoltage,forexample). Any previously logged faults remain in memory and their reporting will return upon exiting the forcing mode. EN1 LTC2928 EN2 EN3 EN4 RT1 HVCC 3.32k SUPPLY BANK 0.047 F VCC 0.1 F RT4 CMP1 CMP2 CMP3 CMP4 SQT2 SQT1 ON V1 V2 V3 V4 MS1 MS2 RT2 RT3 VSEL GND RTMR PTMR STMR VCC REF OVA DONE FLT OV RDIS CAS RST 10k 10k 10k 10k 10k 52.3k 3.3V 1.8V 1.5V 2.5V 23.7k 17.8k 36.5k 10k 2928 TA05 SYSTEM LOGIC Figure 11. Quad Supervisor (No Sequencing) APPLICATIO S I FOR ATIO |
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