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CD54HC74F データシート(PDF) 7 Page - Texas Instruments |
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CD54HC74F データシート(HTML) 7 Page - Texas Instruments |
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7 / 8 page  7 FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS Test Circuits and Waveforms (Continued) trCL tfCL GND VCC GND VCC 50% 90% 10% GND CLOCK INPUT DATA INPUT OUTPUT SET, RESET OR PRESET VCC 50% 50% 90% 10% 50% 90% tREM tPLH tSU(H) tTLH tTHL tH(L) tPHL IC CL 50pF tSU(L) tH(H) trCL tfCL GND 3V GND 3V 1.3V 2.7V 0.3V GND CLOCK INPUT DATA INPUT OUTPUT SET, RESET OR PRESET 3V 1.3V 1.3V 1.3V 90% 10% 1.3V 90% tREM tPLH tSU(H) tTLH tTHL tH(L) tPHL IC CL 50pF tSU(L) 1.3V tH(H) 1.3V CD54HC74, CD74HC74, CD74HCT74 |
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