CLC1003 datasheet(14/16 Pages) CADEKA

14 / 16 page

Data Sheet

www.cadeka.com

The first place to start is to determine the source resis-

tance. If it is very small an additional resistance may need

to be added to keep the values of Rf and Rg to practical

levels. For this analysis we assume that Rt is the total re-

sistance present on the non-inverting input. This gives us

one equation that we must solve:

Rt = Rg||Rf

This equation can be rearranged to solve for Rg:

Rg = (Rt * Rf) / (Rf - Rt)

The other consideration is desired gain (G) which is:

G = (1 + Rf/Rg)

By plugging in the value for Rg we get

Rf = G * Rt

And Rg can be written in terms of Rt and G as follows:

Rg = (G * Rt) / (G - 1)

The complete input offset equation is now only dependent

on the voltage offset and input offset terms given by:

OS =

( )

+ IOS ∗ RT

(

)

And the output offset is:

OS = G ∗

( )

+ I OS ∗ RT

(

)

Noise analysis

The complete equivalent noise circuit is shown in Figure 7.

–

CLC1003

+ –

–

+ –

Figure 7: Complete Equivalent Noise Circuit

The complete noise equation is given by:

o = v

orext + en 1 +

+ ibp∗ RT 1 +

+ ibn∗ RF

(

)

Where Vorext is the noise due to the external resistors and

is given by:

= en 1 +

+ eG ∗

+ e

The complete equation can be simplified to:

= 3 ∗ 4kT ∗ G ∗ RT

(

) + enG

( )

+ 2 ∗ in∗RT

(

)

It’s easy to see that the effect of amplifier voltage noise

is proportionate to gain and will tend to dominate at large

gains. The other terms will have their greatest impact at

large Rt values at lower gains.

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. CADEKA has evaluation

boards to use as a guide for high frequency layout and as

aid in device testing and characterization. Follow the steps

below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB002

CLC1003 in SOT23-5

CEB003

CLC1003 in SOIC-8

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