Data Sheet

©2007-2009 CADEKA Microcircuits LLC

www.cadeka.com

10

can be calculated as above with the desired signal ampli-

tudes using:

The dynamic power is focused primarily within the output

stage driving the load. This value can be calculated as:

Assuming the load is referenced in the middle of the pow-

Figure 4 shows the maximum safe power dissipation in

the package vs. the ambient temperature for the pack-

ages available.

0

0.5

1

1.5

2

-40

-20

0

20

40

60

80

Ambient Temperature (°C)

SOIC-8

Figure 4. Maximum Power Derating

Driving Capacitive Loads

Increased phase delay at the output due to capacitive

loading can cause ringing, peaking in the frequency re-

sponse, and possible unstable behavior. Use a series resis-

prove stability and settling performance. Refer to Figure 5.

+

-

Input

Output

Capacitive Loads

Overdrive Recovery

An overdrive condition is defined as the point when ei-

ther one of the inputs or the output exceed their specified

voltage range. Overdrive recovery is the time needed for

the amplifier to return to its normal or linear operating

point. The recovery time varies, based on whether the

input or output is overdriven and by how much the range

is exceeded. The CLC2059 will typically recover in less

than 5μs from an overdrive condition. Figure 6 shows the

CLC2059 in an overdriven condition.

-20

-10

0

10

20

-10

-5

0

5

10

0

4

8

12

16

20

Time (us)

Output

Input

G = 5

Figure 6. Overdrive Recovery

Layout Considerations

General layout and supply bypassing play major roles

in high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

an aid in device testing and characterization. Follow the

steps below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.