Excelics

EPA030B

PRELIMINARY DATA SHEET

High Performance Heterojunction Dual-Gate FET

••

+18.0dBm TYPICAL OUTPUT POWER

••

19.5dB TYPICAL POWER GAIN AT 12GHz

••

0.3 X 300 MICRON RECESSED “MUSHROOM”

DUAL GATE

••

••

ADVANCED EPITAXIAL DOPING

PROFILE PROVIDES EXTRA HIGH PERFORMANCE

AND HIGH RELIABILITY

••

MIXER, SWITCH, AGC AND TEMPERATURE

COMPENSATION APPLICATIONS

••

Idss SORTED IN 5mA PER BIN RANGE

SYMBOLS

PARAMETERS/TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output Power at 1dB Compression

Vds=6V, Ids=50% Idss, Vg2s=0V

f=12GHz

15.0

18.0

dBm

Gain at 1dB Compression

Vds=6V, Ids=50% Idss, Vg2s=0V

f=12GHz

17.5

19.5

dB

NF

Noise Figure

Vds=3V, Ids=15mA, Vg2s=0V

f=12GHz

1.2

dB

Ga

Associated Gain

Vds=3V, Ids=15mA, Vg2s=0V

f=12GHz

17.5

dB

Idss

Saturated Drain Current

Vds=3V, Vg1s=Vg2s=0V

30

80

115

mA

Gm

Transconductance

Vds=3V, Vg1s=-0.5V, Vg2s=0V

40

70

mS

Vp1

Pinch-off Voltage

Vds=3V, Ids=1.0mA, Vg2s=0V

-1.5

-3.5

V

Vp2

Pinch-off Voltage

Vds=3V, Ids=1.0mA, Vg1s=0V

-1.5

-3.5

V

BVg2d

Gate 2 to Drain Breakdown Voltage

Ig2d=1.0mA, Gate 1 Open

-10

-14

V

BVg1s

Gate 1 to Source Breakdown Voltage

Ig1s=1.0mA, Gate 2 Open

-6

-12

V

Rth

Thermal Resistance (Au-Sn Eutectic Attach)

125

Excelics Semiconductor, Inc., 310 De Guigne Drive, Sunnyvale, CA 94085

Chip Thickness: 75

± 13 microns

All Dimensions In Microns