SN74ACT3631

512

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

8

POST OFFICE BOX 655303

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

CSB

W/RB

ENB

MBB

CLKB

B0 – B35 OUTPUTS

PORT FUNCTION

H

X

X

X

X

In high-impedance state

None

L

L

L

X

X

In high-impedance state

None

L

L

H

L

↑

In high-impedance state

None

L

L

H

H

↑

In high-impedance state

Mail2 write

L

H

L

L

X

Active, FIFO output register

None

L

H

H

L

↑

Active, FIFO output register

FIFO read

L

H

L

H

X

Active, mail1 register

None

L

H

H

H

↑

Active, mail1 register

Mail1 read (set MBF1 high)

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only

for enabling write and read operations and are not related to high-impedance control of the data outputs. If a

port enable is low during a clock cycle, the port-chip select and write/read select can change states during the

setup- and hold-time window of the cycle.

When the output-ready (OR) flag is low, the next data word is sent to the FIFO output register automatically by

the CLKB low-to-high transition that sets the output-ready flag high. When OR is high, an available data word

is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB),

write/read select (W/RB), enable (ENB), and mailbox select (MBB).

synchronized FIFO flags

Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the

flags’ reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate

asynchronously to one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.

Table 4 shows the relationship of each flag to the number of words stored in memory.

Table 4. FIFO Flag Operation

NUMBER OF WORDS IN

FIFO†‡

SYNCHRONIZED

TO CLKB

SYNCHRONIZED

TO CLKA

FIFO†‡

OR

AE

AF

IR

0

L

L

H

H

1 to X

H

LH

H

(X + 1) to [512 – (Y + 1)]

H

HH

H

(512 – Y) to 511

H

HL

H

512

H

H

L

L

† X is the almost-empty offset for AE. Y is the almost-full offset for AF.

‡ When a word is present in the FIFO output register, its previous memory

location is free.