SN74ACT3631

512

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS246G – AUGUST 1993 – REVISED APRIL 1998

15

POST OFFICE BOX 655303

CLKB

IR

B0 – B35

MBB

ENB

CSB

W/RB

OR

CLKA

CSA

W/RA

MBA

ENA

A0 – A35

tsu(EN)

th(EN)

tc

th(EN)

tsu(EN)

tpd(C-IR)

FIFO Full

tc

tsk(1)†

ta

FIFO Output Register

Next Word From FIFO

tw(CLKH)

tw(CLKL)

Write

Low

Low

High

Low

High

th(EN)

tsu(EN)

th(D)

tsu(D)

High

tw(CLKH)

tw(CLKL)

tpd(C-IR)

12

† tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tsk(1), then IR can transition high one CLKA cycle later than shown.

Figure 7. IR-Flag Timing and First Available Write When the FIFO Is Full