SN75176A

DIFFERENTIAL BUS TRANSCEIVER

SLLS100A – JUNE 1984 – REVISED MAY 1995

6

POST OFFICE BOX 655303

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIT +

Positive-going input threshold voltage

VO = 2.7 V,

IO = – 0.4 mA

0.2

V

VIT–

Negative-going input threshold voltage

VO = 0.5 V,

IO = 8 mA

– 0.2‡

V

Vhys

Input hysteresis voltage (VIT + – VIT –)

50

mV

VIK

Enable clamp voltage

II = – 18 mA

– 1.5

V

VOH

High level output voltage

VID = 200 mV,

IOH = – 400 µA,

27

V

VOH

High-level output voltage

ID

,

See Figure 2

OH

µ ,

2.7

V

VOL

Low level output voltage

VID = – 200 mV,

IOL = 8 mA,

045

V

VOL

Low-level output voltage

ID

,

See Figure 2

OL

,

0.45

V

IOZ

High-impedance-state output current

VO = 0.4 V to 2.4 V

±20

µA

II

Line input current

Other input = 0 V,

VI = 12 V

1

mA

II

Line input current

,

See Note 3

VI = – 7 V

– 0.8

mA

IIH

High-level enable input current

VIH = 2.7 V

20

µA

IIL

Low-level enable input current

VIL = 0.4 V

– 100

µA

ri

Input resistance

12

k

Ω

IOS

Short-circuit output current

–15

–85

mA

ICC

Supply current (total package)

No load

Outputs enabled

35

50

mA

ICC

Supply current (total package)

No load

Outputs disabled

26

40

mA

† All typical values are at VCC = 5 V, TA = 25°C.

‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode

input voltage and threshold voltage levels only.

NOTE 3: This applies for both power on and power off. Refer to ANSI Standard EIA/TIA-422-B for exact conditions.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

VID = 1 5Vto1 5V

See Figure 6

21

35

ns

tPHL

Propagation delay time, high-to-low-level output

VID = – 1.5 V to 1.5 V, See Figure 6

23

35

ns

tPZH

Output enable time to high level

See Figure 7

10

30

ns

tPZL

Output enable time to low level

See Figure 7

12

30

ns

tPHZ

Output disable time from high level

See Figure 7

20

35

ns

tPLZ

Output disable time from low level

See Figure 7

17

25

ns