TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

13

POST OFFICE BOX 655303

APPLICATION INFORMATION

gain of VCO and PFD

Figure 16 is a block diagram of the PLL. The

divider N value depends on the input frequency

and the desired VCO output frequency according

characteristics of the device as shown in

Figures 8, 9, 10, and 11 as shown in Figure 16(c).

The parameters for the block diagram with the

units are as follows:

external counter

When a large N counter is required by the

application, there is a possibility that the PLL

response becomes slow due to the counter

response delay time. In the case of a high

frequency application, the counter delay time

should be accounted for in the overall PLL design.

most accurate results, a metal-film resistor is the better choice but a carbon-composition resistor can also be

used with excellent results. A 0.22

µF capacitor should be connected from the BIAS terminal to ground as close

to the device terminals as possible.

hold-in range

From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter

configurations shown in Figure 17 is as follows:

Dw

H ]

0.8 Kp

K

V

K

f

(

R)

Where

(1)

Divider

(KN = 1/N)

PFD

(Kp)

VCO

(KV)

LPF

(Kf)

TLC2933

f REF

VOH

fMAX

fMIN

VIN MIN

VIN MAX

–2

π

2

π

–

π

0

π

Range of

Comparison

VOH

VOL

Kp =

VOH – VOL

4

π

KV =

2

π(fMAX – fMIN)

VIN MAX – VIN MIN

Figure 16. Example of a PLL Block Diagram

(a)

(c)

(b)