TMS320VC549 datasheet(19/60 Pages) TI

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TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing

switching characteristics over recommended operating conditions for a memory read

(MSTRB = 0)†‡ (see Figure 5)

PARAMETER

’549-80

’549-100

’549-120

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

td(CLKL-A)

Delay time, address valid from CLKOUT low§

– 1

td(CLKH-A)

Delay time, address valid from CLKOUT high (transition)¶

– 1

td(CLKL-MSL)

Delay time, MSTRB low from CLKOUT low

– 1

td(CLKL-MSH)

Delay time, MSTRB high from CLKOUT low

– 1

th(CLKL-A)R

Hold time, address valid after CLKOUT low§

– 1

th(CLKH-A)R

Hold time, address valid after CLKOUT high¶

– 1

–1

† Address, PS, and DS timings are all included in timings referenced as address.

‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

§ In the case of a memory read preceded by a memory read

¶ In the case of a memory read preceded by a memory write

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