The levels on these three terminals determine which of the eight antiblooming modes is selected:

MODE

ABS2

ABS1

ABS0

Operation

0LLL

No ABG pulses

1

L

L

H

250-kHz clocking during flyback only

2

L

H

L

1-MHz clocking during flyback only

3

L

H

H

2.2-MHz clocking during flyback only

4

H

L

L

250-kHz continuous clocking

5

H

L

H

500-kHz continuous clocking

6

H

H

L

1-MHz continuous clocking

7

H

H

H

2.2-MHz continuous clocking

TMS3471C

2/3-INCH NTSC TIMER

SOCS028B – AUGUST 1991

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ABIN

29

O

Antiblooming in. ABIN drives the ABG input of the TC240/TC241 CCD image sensors.

ABS0

9

I

ABS1

10

I

ABS2

11

I

BCP1

44

O

Optical black clamp pulse 1

BCP2

1

O

Optical black clamp pulse 2

BCPS0

39

I

The levels on BCPS0 and BCPS1 determine the placement and duration of the BCP1 and BCP2 pulses

relative to the horizontal scan timing (see Figure 4 for the truth table for BCPS0 and BCPS1 and for the

BCPS1

40

I

relative to the horizontal scan timing (see Figure 4 for the truth table for BCPS0 and BCPS1 and for the

corresponding BCP1 and BCP2 pulse placements).

BF

6

O

Burst flag

CBLK

5

O

Composite blank

CLK2M

21

O

2-MHz clock

CP1

3

O

Clamp

CP2

2

O

Clamp

CSYNC

4

O

Composite sync

E/L

42

I

Delay select for S1 and S2,3. When E/L is high, the two serial-transfer pulses occur early relative to the

sample-and-hold pulses SH1 and SH2,3. When E/L is low, the two serial-transfer pulses occur late

relative to the sample-and-hold pulses.

FI

43

O

Field index

GND

33

Ground

GP

15

I

Exposure control: GP gates PS and PI

GT

28

O

TMS3473B parallel-driver MIDSEL input switch

GT1

36

O

Y gate 1

GT2

37

O

Y gate 2

GT3

38

O

Y gate 3

HGATE

20

O

Decoded H count signal. HGATE is a test point and is not used in normal operation.

HIGH

12

I

Not used (tie high)

I/N

13

I

Interlace select. If high, interlace mode is selected; if low, noninterlace mode is selected.

PD

26

O

Power down. A low-logic level on PD causes the device to enter a low power-consumption mode.

PI

30

O

Parallel-image-area gate clock

PS

27

O

Parallel-storage-area gate clock

SB

14

I

Standby-mode select. When SB is high, normal operation is selected; when SB is low, the power-down

mode is selected.

SC

7

O

Subcarrier (3.58 MHz)

SC(90)

8

O

Subcarrier phase shifted by 90 degrees

SH1

32

O

Sample-and-hold pulse 1

SH2,3

31

O

Sample-and-hold pulse 2, 3