TUSB2046A

4-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS404 – DECEMBER 1999

9

POST OFFICE BOX 655303

APPLICATION INFORMATION

USB design notes

The following sections provide block diagram examples of how to implement the TUSB2046A device. Note,

even though no resistors are shown, pullup, pulldown and series resistors must still be used to properly

implement this device. Figure 1 shows a few resistors that must be used for the USB lines, and for a general

reference design, one is available on the TI USB web site at http://www.ti.com/sc/usb.

Figure 6 is a block diagram example of how to connect the external EEPROM if a custom product ID and vendor

ID are desired.

Figure 7 is an example of how to generate the 6-MHz clock signal. Figure 8 shows the EEPROM read operation

timing diagram. Figures 9, 10, and 11 illustrate how to connect the TUSB2046A device for different power source

and port power management combinations.

1 k

Ω

DP0

DM0

EEDATA

TUSB2046A USB Hub

System

Power-On Reset

Regulator

Power

Switching

OVRCUR1 –

OVRCUR4

PWRON1 –

PWRON4

EECLK

RESET

XTAL1

EXTMEM

VCC

GND

DP1 – DP4

DM1 – DM4

GND

Vbus

5 V GND

XTAL2

USB Data lines

and Power to

Downstream

Ports

Bus or Local Power

6-MHz Clock

Signal

4

4

4

4

30

29

4

1

2

6

5

3, 25

7, 28

12, 16, 20, 24

10, 14, 18, 22

11, 15, 19, 23

9, 13, 17, 21

5

8

6

2

4

3

ORG

VCC

VSS

D

Q

C

S

1

EEPROM

3.3 V

26

Figure 6. Typical Application of the TUSB2046A USB Hub

XTAL1

XTAL2

NOTE A: Figure 7 assumes a 6 MHz fundamental crystal that is parallel loaded. The component values of C1, C2 and Rd were determined

using a crystal from Fox Electronics – part number HC49U–6.00MHz30\50\0

±70\20 which means ±30 ppm at 25°C and 50 ppm from

0

°C to 70°C. The characteristics for the crystal are load capacitance (CL) of 20 pF, maximum shunt capacitance (Co) of 7 pF, and the

maximum ESR of 50

Ω. In order to insure enough negative resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the gain,

and Rd = 1.5 kΩ is recommended.

Rd

C2

C1

CL

Figure 7. Crystal Tuning Circuit