TUSB2077A

7-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS414 – MARCH 2000

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

BUSPWR

10

I

Power source indicator. BUSPWR is an active low input that indicates whether the downstream ports

source their power from the USB cable or a local power supply. For the bus-power mode, this pin should

be pulled low, and for the self–powered mode, this pin should be pulled to 3.3 V. Input must not change

dynamically during operation.

DM0

4

I/O

Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.

DM1 – DM7

13, 17, 21, 26,

30, 34, 38

I/O

USB differential data minus. DM1 – DM7 paired with DP1 – DP7 support up to seven downstream USB

ports.

DP0

3

I/O

Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.

DP1 – DP7

14, 18, 22, 27,

31, 35, 39

I/O

USB differential data plus. DP1 – DP7 paired with DM1 – DM7 support up to seven downstream USB

ports.

DP0PUR

2

O

Pull-up resistor connection. When a system reset happens (RESET being driven to low, but not USB

reset) or any logic level change on BUSPWR terminal, DP0PUR output is inactive (floating) until the

internal counter reaches a 15 ms time period. After the counter expires, DP0PUR is driven to the VCC

(3.3 V) level thereafter until the next system reset event occurs or there is a BUSPWR logic level

change.

EECLK

7

O

EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK pin is

disabled and should be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state

serial clock output to the EEPROM with a 100

µA internal pulldown.

EEDATA/

GANGED

8

I/O

EEPROM serial data/power management mode indicator. When EXTMEM is low, EEDATA/

GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100

µA

pulldown. When EXTMEM is high, EEDATA/GANGED selects between gang or per port power

over–current detection for the downstream ports. This standard TTL input must not change dynamically

during operation.

EXTMEM

47

I

EEPROM read enable. When EXTMEM is high, the serial EEPROM interface of the device is disabled.

When EXTMEM is low, terminals 7 and 8 are configured as the clock and data pins of the serial

EEPROM interface, respectively.

GND

5, 24, 43

Ground. GND terminals must be tied to ground for proper operation.

HUBCFG†

40

O

Hub configured. Used to control LED indicator. When the hub is configured, HUBCFG is high, which

can be used to turn on a green LED. When the hub is not configured, HUBCFG is low, which can be

used to turn on a red LED.

MODE

48

I

Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the

internal core of the chip and 6-MHz crystal or oscillator can used. When MODE is high, the clock on

XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source

can be used.

OVRCUR1 –

OVRCUR7

12, 16, 20, 25,

29, 33, 37

I

Over-current input. OVRCUR1 – OVRCUR7 are active low. For per-port over current detection, one

over-current input is available for each of the seven downstream ports. In the ganged mode, any

OVRCUR input may be used and all OVRCUR pins should be tied together. OVRCUR pins have noise

filtering logic.

PORTPWR†

41

O

Any port powered. Used to control LED indicator. When any port is powered on, PORTPWR is high,

which can be used to turn on a green LED. When all ports are off, PORTPWR is low, which can be used

to turn on a red LED.

PORTDIS†

42

O

No ports disabled. PORTDIS is used for LED indicator control. When no port is disabled, PORTDIS is

high, which can be used to turn on a green LED. When any port is disabled, PORTDIS is low, which

can be used to turn on a red LED.

PWRON1 –

PWRON7

11, 15, 19, 23,

28, 32, 36

O

Power-on/-off control signals. PWRON1 – PWRON7 are active low, push-pull outputs that enables the

external power switch device. Push-pull outputs eliminate the pull-up resistors which are required by

for open-drain outputs. However, the external power switches that connect to these pins must be able

to operate with 3.3-V inputs because these outputs cannot drive 5-V signals.

RESET

6

I

Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When

RESET is asserted, all logic is initialized. Generally, a reset with a pulse width between 100

µs and 1

ms is recommended after 3.3-V VCC reaching its 90%. The clock signal must be active during the last

60

µs of the reset window.