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TUSB3200 データシート(PDF) 75 Page - Texas Instruments |
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TUSB3200 データシート(HTML) 75 Page - Texas Instruments |
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75 / 93 page  A–27 A.5.3.2 Adaptive Clock Generator Frequency Register (Byte 1) (ACGFRQ1 – Address FFE6h) The adaptive clock generator frequency register (byte 1) contains the middle byte of the 24-bit ACG frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ15 FRQ14 FRQ13 FRQ12 FRQ11 FRQ10 FRQ9 FRQ8 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(15:8) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG frequency synthesizer to obtain the desired CODEC master clock output (MCLKO) signal frequency. A.5.3.3 Adaptive Clock Generator Frequency Register (Byte 2) (ACGFRQ2 – Address FFE5h) The adaptive clock generator frequency register (byte 2) contains the most significant byte of the 24-bit ACG frequency value. Bit 7 6 5 4 3 2 1 0 Mnemonic FRQ23 FRQ22 FRQ21 FRQ20 FRQ19 FRQ18 FRQ17 FRQ16 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FRQ(23:16) ACG frequency The ACG frequency bit values are set by the MCU to program the ACG frequency synthesizer to obtain the desired CODEC master clock output (MCLKO) signal frequency. A.5.3.4 Adaptive Clock Generator MCLK Capture Register (Low Byte) (ACGCAPL – Address FFE4h) The adaptive clock generator MCLK capture register (low byte) contains the least significant byte of the 16-bit CODEC master clock (MCLK) signal cycle count that is captured each time a USB start of frame (SOF) occurs. Basically the value of a16-bit free running counter, which is clocked with the MCLK signal, is captured at the beginning of each USB frame. The source of the MCLK signal used to clock the 16-bit timer can be selected to be either the MCLKO signal or the MCLKO2 signal. See section 2.2.10 for the operation details of the adaptive clock generator. Bit 7 6 5 4 3 2 1 0 Mnemonic CAP7 CAP6 CAP5 CAP4 CAP3 CAP2 CAP1 CAP0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 CAP(7:0) ACG MCLK capture The ACG MCLK capture bit values are updated by hardware each time a USB start of frame occurs. This register contains the least signification byte of the 16-bit value. |
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