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3/11/97

SPT7824

TYPICAL INTERFACE CIRCUIT

The SPT7824 requires few external components to achieve

the stated operation and performance. Figure 2 shows the

typical interface requirements when using the SPT7824 in

normal circuit operation. The following section provides a

description of the pin functions and outlines critical perfor-

mance criteria to consider for achieving the optimal device

performance.

POWER SUPPLIES AND GROUNDING

The SPT7824 requires -5.2 V and +5 V analog supply

intended to reduce the transient noise injected into the analog

sible to the device. The connection between the beads and

the SPT7824 should not be shared with any other device.

Each power supply pin should be bypassed as closely as

possible to the device. Use 0.1

0.01

Figure 2 - Typical Interface Circuit

AGND and DGND are the two grounds available on the

SPT7824. These two internal grounds are isolated on the

device. The use of ground planes is recommended to achieve

return path (40 mA typical) and for the return path for all digital

output logic interfaces. AGND and DGND should be sepa-

rated from each other and connected together only at the

device through a ferrite bead.

A Schottky or hot carrier diode connected between AGND

power supply sequencing latch-up conditions. Using the

recommended interface circuit shown in figure 2 will provide

optimum device performance for the SPT7824.

D10 (Overrange)

D9 (MSB)

D8

D7

D6

D5

D4

D3

D2

D1

D0 (LSB)

- 5.2 V

COARSE

A/D

ANALOG

PRESCALER

SUCCESSIVE

INTERPOLATION

STAGE # 1

SUCCESSIVE

INTERPOLATION

STAGE # N

4

IC1

(REF-03)

6

5

2

4

+ 5 V

+

VOUT

Trim

GND

VIN

1

µF

C1

.01

µF

+-

10 k

Ω

1

32

4

8

7

6

10 k

Ω

30 k

Ω

30 k

Ω

C19

1

µF

+

+5 V

.01

µF

.01

µF

CLK

VIN

VFT

VST

VRM

VSB

VFB

R

2R

2R

2R

2R

R

+

1

µF

CLK

VIN

IC2

OP-07

10

µF

10

µF

+

D1

C10

.01

µF

+

(TTL)

(

±2 V)

+2.5 V

-2.5 V

FB

+5 V

AGND

DGND

-5.2 V

(Analog)

(Analog)

C11

.01

µF

R1

100

Ω

± 2.5 V Max

C2

.01

µF

C3

.01

µF

C4

.01

µF

C5

.01

µF

C6

.1

µF

C7

.1

µF

C8

C9

Notes to prevent latch-up due to power sequencing:

1)

D1 = Schottky or hot carrier diode, P/N IN5817.

2)

FB = Ferrite bead, Fair Rite P/N 2743001111

to be mounted as close to the device as possible. The ferrite bead to the

ADC connection should not be shared with any other device.

3)

C1-C11 = Chip cap (recommended) mounted as close to the device's pin

as possible.

4)

Use of a separate supply for VCC and DVCC is not recommended.

5)

R1 provides current limiting to 45 mA.

6)

C6, C7, C8 and C9 should be ten times larger than C10 and C11.

7)

C8 = C9 = a 0.1

µF cap in parallel with a 4.7 µF cap.