2

2/15/01

SPT9713

Note: 1. Operation at any Absolute Maximum Rating is not implied. See

Electrical Specifications for proper nominal applied conditions

in typical applications.

Supply Voltages

A/D Ground Voltage Differential ........................... 0.5 V

Input Voltages

Digital Input Voltage

Control Amp Input Voltage Range ............... 0 V to –4 V

Output Currents

Internal Reference Output Current .................... 500 µA

Control Amplifier Output Current ..................... ±2.5 mA

Temperature

Operating Temperature .......................... –40 to +85 °C

Junction Temperature ...................................... +150 °C

Lead, Soldering (10 seconds) ......................... +300 °C

Storage ................................................ –65 to +150 °C

ELECTRICAL SPECIFICATIONS

TEST

TEST

SPT9713A

SPT9713B

PARAMETERS

CONDITIONS

LEVEL

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DC Performance

Resolution

12

12

Bits

Differential Linearity

I

±0.5

±0.75

±1.0

±1.25

LSB

Differential Linearity

Max at Full Temp.

VI

±1.5

±2.0

LSB

Integral Linearity

Best Fit

I

±0.75

±1.0

±1.0

±1.5

LSB

Integral Linearity

Max at Full Temp.

VI

±1.75

±2.0

LSB

Output Capacitance

+25 °C

V

10

10

pF

+25 °C

I

1.0

5.0

1.0

5.0

% FS

Full Temp.

VI

8.0

8.0

% FS

Gain Error Tempco

Full Temp.

V

150

150

PPM/°C

Zero-Scale Offset Error

+25 °C

I

0.5

2.5

0.5

2.5

µA

Full Temp.

VI

5.0

5.0

µA

Offset Drift Coefficient

Full Temp.

V

0.01

0.01

µA/°C

Output Compliance Voltage

+25 °C

IV

–1.2

+2.0

–1.2

+2.0

V

Equivalent Output Resistance

+25 °C

IV

0.8

1.0

1.2

0.8

1.0

1.2

k

Ω

Dynamic Performance

Conversion Rate

+25 °C

IV

100

100

MWPS

+25 °C

V

13

13

ns

+25 °C

V

2

2

ns

+25 °C

V

15

15

pV-s

+25 °C

V

20.48

20.48

mA

+25 °C

1.23 MHz; 10 MWPS

2 MHz Span

V

70

70

dBc

5.055 MHz; 20 MWPS

2 MHz Span

V

68

68

dBc

10.1 MHz; 50 MWPS

2 MHz Span

V

68

68

dBc

16 MHz; 40 MWPS

10 MHz Span

V

68

68

dBc

Rise Time / Fall Time

V2

2

ns

1

2

3

Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band.

4

Glitch is measured as the largest single transient.

5

6

SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window,

which is centered at the fundamental frequency and covers the indicated span.