ADM2914 datasheet(11/16 Pages) AD

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ADM2914

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Next, consider a −12 V input, which is specified with a ±20%

input. The threshold accuracy required by the supply is chosen

to be within ±5% of the −12 V rail. Therefore, the overvoltage

threshold is set to −13.5 V, and the undervoltage threshold is

−10.5 V. The negative voltage scheme configuration requires

that the 1 V reference voltage be accounted for in Equation 1 to

Equation 3. The 1 V reference voltage is subtracted from VM,

VUV, and VOV, and the absolute value of the result is taken.

Equation 1 becomes

(

)

(

)

(

)

kΩ

)

(

≈

−

Insert the value of RZ into Equation 2.

(

)

(

)

(

)

kΩ

)

(

≈

−

To calculate RX, insert the value of RZ and RY into Equation 3.

(

) (

)

MΩ

kΩ

≈

−

POWER-UP AND POWER-DOWN

On power-up, when VCC reaches 1 V, the active low UV output

is asserted, and the OV output pulls up to VCC. When the vol-

tage on the VCC pin reaches 1 V, the ADM2914 is guaranteed to

assert UV low and OV high. When VCC exceeds 1.9 V (minimum),

the VHx and VLx inputs take control. When VCC and each of

the VHx inputs are valid, an internal timer begins. Subsequent

to an adjustable time delay, UV weakly pulls high.

UV/OV TIMING CHARACTERISTICS

UV is an active low output. It is asserted when any of the four

monitored voltages is below its associated threshold. When the

voltage on the VCC pin is above 2 V, an internal timer holds

UV low for an adjustable period, tUOTO, after the voltage on all

the monitoring rails rises above their thresholds. This allows

time for all monitored power supplies to stabilize after power-

up. Similarly, any monitored voltage that falls below its threshold

initiates a timer reset, and the timer starts again when all the

monitoring rails rise above their thresholds.

The UV and

TIMER CAPACITOR SELECTION

OV outputs are held asserted after all faults have

cleared for an adjustable timeout period, determined by the

value of the external capacitor attached to the TIMER pin.

The UV and

F/sec

)

)(

115

)(

(

−

UOTO

TIMER

OV timeout period on the ADM2914 is programma-

ble via the external timer capacitor, CTIMER, placed between the

TIMER pin and ground. The timeout period, tUOTO, is calculated

using the following equation:

Refer to Figure 15 in the Typical Performance Characteristics

section, which illustrates the delay time as a function of the

timer capacitor value. A minimum capacitor value of 10 pF is

required. The chosen timer capacitor must have a leakage current

that is less than the 1.3 µA TIMER pin charging current. To

bypass the timeout period, connect the TIMER pin to VCC.

tUOD

tUOTO

VHx

VUOT

VHx

VHx MONITOR TIMING (TIMER PIN TIED TO VCC)

VHx MONITOR TIMING

WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE,

VHx WILL TRIGGER AN OVERVOLTAGE CONDITION.

Figure 21. VHx Positive Voltage Monitoring Timing Diagram

tUOD

tUOTO

VLx

VUOT

VLx

VLx MONITOR TIMING (TIMER PIN TIED TO VCC)

VLx MONITOR TIMING

WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE,

VLx WILL TRIGGER AN UNDERVOLTAGE CONDITION.

Figure 22. VLx Positive Voltage Monitoring Timing Diagram

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