SMM153

Preliminary Information

Summit Microelectronics, Inc

2.0 8/12/2008

8

DEVICE OPERATION

POWER SUPPLY

The SMM153 can be powered by a 2.7V to 5.5V input

to the VDD pin (Figure 1).

See Figure 4 as an

example.

VOLTAGE REFERENCE

The SMM153 uses an internal voltage reference,

VREF of 1.25V. Total accuracy of VREF is ±1.0% over

temperature and supply variations.

MODES OF OPERATION

The SMM153 has three basic modes of operation:

UV/OV monitoring, differential output voltage sensing

and input current measuring mode. A detailed

description of each mode and feature follows and can

also be found in Application Note 68.

MONITOR

The SMM153 monitors the COMP1 and COMP2 pins.

COMP1 and COMP2 are high impedance inputs, each

connected internally to a comparator and compared

against the programmable internal reference voltage.

Each comparator can be independently programmed

to monitor for either an UV or an OV. The monitor level

is set externally with a resistive voltage divider. The

COMPx pins can be connected to Vin, Vout or any

voltage that needs to be monitored. The internal

comparators COMP1/2 are compared to VREF, so the

voltage dividers are set above or below the

programmed VREF level depending on whether

monitoring UV or OV. As an example, with VREF set

to 1.25V, to monitor an OV of 1.7V on COMP1 and a

UV of 1.3V on COMP2, the voltage divider resistors

are:

For OV, RUpper = 1.37k, 1% RLower = 3.83k, 1%.

For UV, RUpper = 1.02k, 1% RLower = 25.5k, 1%.

The part can be programmed to trigger the FAULT#

pin when either COMPx comparator has exceeded the

UV or OV setting. The FAULT# output of the SMM153

is active as long as the triggering limit remains in a

fault condition. When either of the COMP1 or COMP2

inputs are in fault, the open-drain FAULT# output will

be pulled low.

GENERAL-PURPOSE INPUTS/OUTPUTS

The four integrated GPIOs are open drain type

outputs. The pins should be pulled up externally to

voltages ranging from 2.0V to 12V. Each I/O has Non-

volatile memory setting associated with it that

determines the power-on state of the pin. Additionally,

the I/Os have a command bit that when written takes

overrides the NV setting and sets the pin either high or

low. The I/Os also have status bits to read the state of

the pin as high or low. The command/status register

for each I/O is addressed separately alleviating the

need for the host controller to remember the state of

the other I/Os when writing commands. More

information can be found in Application Note 69.

STATUS REGISTER

A status register exists for I

the COMP1 and COMP2 inputs. Two bits in this status

register reflect the current state of the inputs (1 = fault,

0 = no fault). Two additional bits show the state of the

inputs latched by the FAULT# event (i.e. FAULT#

output going active) programmed in the configuration.

More information can be found in Application Note 69.

FAULTS

When either of the COMP1 or COMP2 inputs are in

fault, the open-drain FAULT# output will be pulled low.

The FAULT# is triggered only on the leading edge of a

Fault. That is, a latched fault can be cleared while the

Fault yet exists.

WRITE PROTECTION

Write protection for the SMM153 is located in a volatile

register where the power-on state is defaulted to write

protect. There are separate write protect modes for the

configuration registers and memory. In order to

the write protection register.

Other codes will enable write protection. For example,

allow writes to the memory but not to the configuration

registers. The SMM153 also features a Write Protect

pin (WP input) which, when asserted, prevents writing

to the configuration registers and EE memory. In

addition to these two forms of write protection there is

a

configuration

register

lock

bit

which,

once

programmed, does not allow the configuration

registers to be changed.

A2, A1, A0

The address bits A[2:0] can be hard wired High or Low

or may be left open (High-Z) to allow for a total of 21

distinct device addresses. When floating, the inputs

can tolerate the amount of leakage as described by

down resistor is sufficient to set a High or Low logic

level.

APPLICATIONS INFORMATION