CPC7594MATR datasheet(16/20 Pages) CLARE

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CPC7594

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R03

As an input, the TSD pin is utilized to place the

CPC7594 into the “All-Off” state by simply pulling the

input to a logic low. For applications using low-voltage

logic devices (lower than VDD), Clare recommends the

use of an open-collector or an open-drain type output

to control TSD. This avoids sinking the TSD pull up bias

current to ground during normal operation when the

all-off state is not required. In general, Clare

recommends all applications use an open-collector or

open-drain type device to drive this pin.

Unlike the CPC7584, driving TSD to a logic 1 or tying

this pin to VCC will not prevent normal operation of the

thermal shutdown circuitry inside the CPC7594. As a

result the TSD pin may be held at a logic high.

However, the CPC7594 TSD pin has only two

recommended operating states when it is used as an

input control. A logic 0, which forces the device to the

all-off state and a high impedance (Z) state for normal

operation. This requires the use of an open-collector

or open-drain type buffer.

2.6 Ringing Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off,

the ringing switch is designed to delay the change in

state until the next zero-crossing. Once on, the switch

requires a zero-current cross to turn off, and therefore

should not be used to switch a pure DC signal. The

switch will remain in the on state no matter the logic

input until the next zero crossing. These switching

characteristics will reduce and possibly eliminate

overall system impulse noise normally associated with

ringing switches. See Clare’s application note AN-144,

Impulse Noise Benefits of Line Card Access Switches for

more information. The attributes of ringing switch SW4

may make it possible to eliminate the need for a

zero-cross switching scheme. A minimum impedance

of 300

Ω in series with the ringing generator is

recommended.

2.7 Power Supplies

Both a +5 V supply and battery voltage are connected

to the CPC7594. Switch state control is powered

exclusively by the +5 V supply. As a result, the

CPC7594 exhibits extremely low power consumption

during active and idle states.

Although battery power is not used for switch control, it

is required to supply trigger current for the integrated

internal protection circuitry SCR during fault

conditions. This integrated SCR is designed to

activate whenever the voltage at TBAT or RBAT drops 2

to 4 V below the applied voltage on the VBAT pin.

Because the battery supply at this pin is required to

source trigger current during negative overvoltage

fault conditions at tip and ring, it is important that the

net supplying this current be a low impedance path for

high speed transients such as lightning. This will

permit trigger currents to flow enabling the SCR to

activate and thereby prevent a fault induced negative

overvoltage event at the TBAT or RBAT nodes.

2.8 Battery Voltage Monitor

The CPC7594 also uses the VBAT voltage to monitor

battery voltage. If system battery voltage is lost, the

CPC7594 immediately enters the all-off state. It

remains in this state until the battery voltage is

restored. The device also enters the all-off state if the

battery voltage rises more positive than about –10 V

with respect to ground and remains in the all-off state

until the battery voltage drops below approximately

–15 V with respect to ground. This battery monitor

feature draws a small current from the battery (less

than 1

μA typical) and will add slightly to the device’s

overall power dissipation.

This monitor function performs properly if the

CPC7594 and SLIC share a common battery supply

origin. Otherwise, if battery is lost to the CPC7594 but

not to the SLIC, then the VBAT pin will be internally

biased by the potential applied at the TBAT or RBAT

pins via the internal protection circuitry SCR trigger

current path.

2.9 Protection

2.9.1 Diode Bridge/SCR

The CPC7594 uses a combination of current limited

break switches, a diode bridge/SCR clamping circuit,

and a thermal shutdown mechanism to protect the

SLIC device or other associated circuitry from damage

during line transient events such as lightning. During a

positive transient condition, the fault current is

conducted through the diode bridge to ground via

FGND. Voltage is clamped to a diode drop above

ground. During a negative transient of 2 to 4 V more

negative than the voltage source at VBAT, the SCR

conducts and faults are shunted to FGND via the SCR

or the diode bridge.

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