ICS8735-21

700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR

IDT™ / ICS™ 3.3V LVPECL ZERO DELAY CLOCK GENERATOR

9

ICS8735AM-21 REV. A JULY 31, 2008

Parameter Measurement Information, continued

Output Duty Cycle/Pulse Width/Period

Propagation Delay

Application Information

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1k

Ω resistor can be tied from CLK to

ground.

FB_IN/nFB_IN Inputs

For applications not requiring the use of the differential input, both

FB_IN and nFB_IN can be left floating. Though not required, but for

additional protection, a 1k

Ω resistor can be tied from FB_IN to

ground.

Outputs:

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

t

PW

t

PERIOD

t

PW

t

PERIOD

odc =

x 100%

nQ, nQFB

Q, QFB

t

PD

nCLK

CLK

nQ, nQFB

Q, QFB