AT90SCR100 datasheet(95/433 Pages) ATMEL

95 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows

the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available

for the OC0B pin (See Table 13-3 on page 99). The actual OC0x value will only be visible on the

port pin if the data direction for the port pin is set as output. The PWM waveform is generated by

setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and

clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes

from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform

generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

13.1.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match

between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 13-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x

and TCNT0.

OC nxPWM

fclk_I/O

N 256

⋅

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