ATmega325P datasheet(61/364 Pages) ATMEL

61 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

12.3.3

EIFR – External Interrupt Flag Register

• Bit 7 – PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set

(one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

This bit is reserved bit in ATmega325P and will always be read as zero.

• Bit 6 – PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT24:16 pin triggers an interrupt request, PCIF2 becomes set

(one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

This bit is reserved bit in ATmega325P and will always be read as zero.

• Bit 5 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 4 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

Bit

543

0x1C (0x3C)

PCIF3

PCIF2

PCIF1

PCIF0

–

INTF0

EIFR

Read/Write

R/W

Initial Value

ATmega325P データシート(PDF) 61 Page - ATMEL Corporation

ATmega325P データシート(HTML) 61 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード

リンク URL

ATmega325P データシート(PDF) 61 Page - ATMEL Corporation

ATmega325P データシート(HTML) 61 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシート ダウンロード

リンク URL

データシートダウンロード