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ATmega324PA データシート(PDF) 21 Page - ATMEL Corporation |
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ATmega324PA データシート(HTML) 21 Page - ATMEL Corporation |
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21 / 468 page ![]() 21 8152G–AVR–11/09 ATmega164PA/324PA/644PA/1284P The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the ATmega164PA/324PA/644PA/1284P are all accessible through all these addressing modes. The Register File is described in ”General Pur- pose Register File” on page 13. Figure 7-2. Data Memory Map for ATmega164PA/324PA/644PA/1284P 7.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk CPU cycles as described in Figure 7-3. Figure 7-3. On-chip Data SRAM Access Cycles 32 Registers 64 I/O Registers Internal SRAM (1024/2048/4096/16384x 8) 0x0000 - 0x001F 0x0020 - 0x005F 0x04FF/0x08FF/0x10FF/0x40FF 0x0060 - 0x00FF Data Memory 160 Ext I/O Reg. 0x0100 clk WR RD Data Data Address Address valid T1 T2 T3 Compute Address CPU Memory Access Instruction Next Instruction |
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