HT95R23 datasheet(22/53 Pages) HOLTEK

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HT95R23

Rev. 1.00

March 25, 2008

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter requires microcontroller

attention, their corresponding interrupt will enforce a

temporary suspension of the main program allowing the

microcontroller to direct attention to their respective

needs. Each device contains a single external interrupt

and single internal timer interrupt functions. The exter-

nal interrupt is controlled by the action of the external

INT pin, while the internal interrupt are controlled by

Timer/Event Counter overflow, a Real Time Clock over-

flow, a DTMF reciever valid character reception etc.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by two interrupt

control registers, INTC0 and INTC1, located in the Data

Memory. By controlling the appropriate enable bits in

this register each individual interrupt can be enabled or

disabled. Also when an interrupt occurs, the corre-

sponding request flag will be set by the microcontroller.

The global enable flag if cleared to zero will disable all

interrupts.

Interrupt Operation

A Timer/Event Counter overflow, the reception of a valid

DTMF character etc. or the external interrupt line being

pulled low will all generate an interrupt request by set-

ting their corresponding request flag, if their appropriate

interrupt enable bit is set. When this happens, the Pro-

gram Counter, which stores the address of the next in-

struction to be executed, will be transferred onto the

stack. The Program Counter will then be loaded with a

new address which will be the value of the correspond-

ing interrupt vector. The microcontroller will then fetch

its next instruction from this interrupt vector. The instruc-

tion at this vector will usually be a JMP statement which

will take program execution to another section of pro-

gram which is known as the interrupt service routine.

Here is located the code to control the appropriate inter-

rupt. The interrupt service routine must be terminated

with a RETI statement, which retrieves the original Pro-

gram Counter address from the stack and allows the

microcontroller to continue with normal execution at the

point where the interrupt occurred.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the accompanying

diagram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

T i m e r / E v e n t C o u n t e r 1 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

I N T C 0 R e g i s t e r

M a s t e r I n t e r r u p t G l o b a l E n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

b 7

b 0

E T 0 I E E I

E M I

T i m e r / E v e n t C o u n t e r 0 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 0 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

E I F

T 0 F

E T 1 I

T 1 F

E x t e r n a l I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

E x t e r n a l I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e r / E v e n t C o u n t e r 1 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

N o t i m p l e m e n t e d , r e a d a s " 0 "

Interrupt Control 0 Register

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