Production Data Rev 1.0

WM2616

WOLFSON MICROELECTRONICS LTD

7

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to

analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input

voltage and the input code according to the following relationship:

Output voltage =

(

)

4096

CODE

V

2

REFIN

INPUT

OUTPUT

1111

1111

1111

( )

4096

4095

V

2

REF

:

:

1000

0000

0001

( )

4096

2049

V

2

REF

1000

0000

0000

( )

REF

REF

V

4096

2048

V

2

=

0111

1111

1111

( )

4096

2047

V

2

REF

:

:

0000

0000

0001

( )

4096

1

V

2

REF

0000

0000

0000

0V

POWER ON RESET

An internal power-on-reset circuit resets the DAC register to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k

Ω

load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of code.

The REFIN pin has an input resistance of 10M

Ω and an input capacitance of typically 5pF. The

reference voltage determines the DAC full-scale output.

SERIAL INTERFACE

Explanation of data transfer:

First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the

data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits

have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be

moved to the DAC latch which updates the voltage output to the new level.

The serial interface of the device can be used in two basic modes:

•

four wire (with chip select)

•

three wire (without chip select)

Using chip select (four wire mode), it is possible to have more than one device connected to the serial

port of the data source (DSP or microcontroller). If there is no need to have more than one device on the

serial bus, then NCS can be tied low.

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

MHz

20

t

t

1

min

WCL

min

WCH

=

+

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling

time to 12 bits limits the update rate for large input step transitions.