WM2617

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.1 October 2000

6

DEVICE DESCRIPTION

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to

analogue voltage levels (see Block Diagram). The output voltage is determined by the reference

input voltage and the input code according to the following relationship:

Output voltage =

()

1024

code

V

2

REF

INPUT

OUTPUT

11

1111

1111

()

1024

1023

V

2

REF

::

10

0000

0001

()

1024

513

V

2

REF

10

0000

0000

()

REF

REF

V

1024

512

V

2

=

01

1111

1111

()

1024

511

V

2

REF

::

00

0000

0001

()

1024

1

V

2

REF

00

0000

0000

0V

POWER ON RESET

An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a

2k

Ω load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of

code. The REFIN input resistance is 10M

Ω and the REFIN input capacitance is typically 5pF. The

reference voltage determines the DAC full-scale output.

SERIAL INTERFACE

When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data

clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the

input register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then

transfers the data to the DAC latch. When NCS is high, input data cannot be clocked into the

input register (see Table 2).

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

MHz

20

t

t

1

min

WCL

min

WCH

=

+

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC

settling time to 10 bits limits the update rate for large input step transitions.

SOFTWARE CONFIGURATION OPTIONS

The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the

10-bit data word. D15-D12 hold the programmable options which are summarized in Table 3.

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Program Bits

New DAC value (10 bits)

x

x

Table 2 Register Map