WM8191 datasheet(24/27 Pages) WOLFSON

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WM8191

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 3.1 April 2001

BIT

NAME(S)

DEFAULT

DESCRIPTION

Determines the output data format.

1:0

MUXOP[1:0]

00 = 14-bit parallel

01 = 8-bit multiplexed (8+6 bits)

10 = 7-bit multiplexed mode (7+7 bits)

11 = 4-bit multiplexed mode (4+4+4+2

bits)

2INVOP

Digitally inverts the polarity of output data.

0 = negative going video gives negative going output,

1 = negative going video gives positive going output data.

VRLCEXT

When set powers down the RLCDAC, changing its output to Hi-Z, allowing

VRLC/VBIAS to be externally driven.

RLCDACRNG

Sets the output range of the RLCDAC.

0 = RLCDAC ranges from 0 to AVDD (approximately),

1 = RLCDAC ranges from 0 to VRT (approximately).

Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC

clock period = 3 MCLK periods.

Setup

7:6

DEL[1:0]

00 = Minimum latency

01 = Delay by one ADC clock

period

10 = Delay by two ADC clock periods

11 = Delay by three ADC clock

periods

3:0

RLCV[3:0]

1111

Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal

reference voltage or Reset Level Clamp voltage. See Electrical

Characteristics section for ranges.

CDS mode reset timing adjust.

5:4

CDSREF[1:0]

00 = Advance 1 MCLK period

01 = Normal

10 = Retard 1 MCLK period

11 = Retard 2 MCLK periods

Monochrome mode channel select.

Setup

7:6

CHAN[1:0]

00 = Red channel select

01 = Green channel select

10 = Blue channel select

11 = Reserved

Software

Reset

Any write to Software Reset causes all cells to be reset.

Auto-cycle

Reset

Any write to Auto-cycle Reset causes the auto-cycle counter to reset

to RINP.

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