X25C02PI datasheet(5/14 Pages) XICOR

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X25C02

Figure 1. Read Operation Sequence

Operational Notes

The X25C02 powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on

CS is required to

enter an active state and receive an instruction.

• SO pin is high impedance.

• The “write enable” latch is reset.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

• The “write enable” latch is reset upon power-up.

• A WREN instruction must be issued to set the “write

enable” latch.

•

CS must come HIGH at the proper clock count in

order to start a write cycle.

The “write enable” latch is reset when

WP is brought LOW.

Figure 2. Set Write Enable Latch Sequence

0123456789

10 11

12 13 14 15 16 17 18 19 20 21 22

3843 FHD F04.1

76543210

DATA OUT

SCK

MSB

HIGH IMPEDANCE

INSTRUCTION

BYTE ADDRESS

01234567

3843 FHD F05.1

SCK

HIGH IMPEDANCE

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